1. Field of the Invention
This invention relates to operational amplifiers, and more particularly, to a rail-to-rail type of operational amplifier based on a common-source amplifier which is devised in such a manner as to allow a low offset voltage and an improved bandwidth. slew rate, and phase margin.
2. Description of Related Art
A conventional rail-to-rail type of input/output (I/O) operational amplifier is composed of a CMOS (complementary metal-oxide semiconductor) transistor, a common-source amplifier, a current-summing amplifier, and an AB-class output stage. The common-source amplifier has a threshold voltage equal to V.sub.gs +V.sub.sat, where V.sub.gs is the potential difference between gate and source, and V.sub.sat is the saturation voltage of the transistor. Therefore, when the common-mode input voltages reach a level nearly equal to the source DC bias V.sub.SS or the drain DC bias V.sub.DD, the operational amplifier will be subjected to a current transient that causes an increase in the input DC offset voltage, thereby affecting the performance of the operational amplifier. This drawback will be described in more detail in the following with reference to FIG. 1.
FIG. 1 is a schematic circuit diagram of a conventional rail-to-rail type of operational amplifier. This operational amplifier includes two sets of common-source differential input units for receiving two input voltages V.sub.i.sup.+ ; and V.sub.i.sup.-, one input unit consisting of a pair of NMOS transistors 105, 106 and the other consisting of a pair of PMOS transistors 107, 108. The gate of the NMOS transistor 105 and the gate of the PMOS transistor 107 are connected to a common node which is connected to the first input voltage V.sub.i.sup.+ ; and in a similar manner, the gate of the NMOS transistor 106 and the gate of the PMOS transistor 108 are connected to a common node which is connected to the second input voltage V.sub.i.sup.-. The drain of the NMOS transistor 105 outputs a differential current .DELTA.i.sub.11.sup.+, while the drain of the NMOS transistor 106 outputs a differential current .DELTA.i.sub.11.sup.-. These two differential currents .DELTA.i.sub.11.sup.+ and .DELTA.i.sub.11.sup.- are fed together to a first current-summing circuit 10 to be summed therein. Similarly, the drain of the PMOS transistor 107 outputs a differential current .DELTA.i.sub.12.sup.+, while the drain of the PMOS transistor 108 outputs a differential output current .DELTA.i.sub.11.sup.-. These two differential output currents .DELTA.i.sub.12.sup.+ and .DELTA.i.sub.l2.sup.- are fed to a second current-summing circuit 12 to be summed therein. The potential difference between the output of the first current-summing circuit 10 and the output of the second current-summing circuit 12, as designated by V1, is fed to a buffer circuit 14. The output of the buffer circuit 14 is coupled to an AB-class output circuit consisting of a PMOS transistor 134 and an NMOS transistor 135. In response to the output of the buffer circuit 14, the AB-class output circuit will produce an output voltage V.sub.o1 which is taken as the output of the operational amplifier. The buffer circuit 14 uses a source follower for the biasing so as to increase the input impedance thereof. The AB-class output circuit acts as a buffer amplifier with one unit gain.
In the foregoing operational amplifier, if the DC bias for the differential currents .DELTA.i.sub.12.sup.+ and .DELTA.i.sub.12.sup.- causes the generation of I.sub.2 =2 .mu.A (micro-ampere), the sum of the two current I.sub.1 +I.sub.2 should be raised to about 20 .mu.A in order to keep the variation of the potential difference V1 that is affected by the offset voltage to less than 10%. In this case, the DC bias for the differential currents .DELTA.i.sub.11.sup.+ and .DELTA.i.sub.11.sup.- should cause the generation of I.sub.1 =18 .mu.A. Further, when the common-mode input voltages V.sub.i.sup.+, V.sub.i.sup.- are raised to a level nearly equal to the drain DC bias V.sub.DD, the PMOS transistors 107, 108 will be switched OFF, causing the differential currents .DELTA.i.sub.12.sup.+ and .DELTA.i.sub.l2.sup.- to disappear and thus the potential difference V1 to rise. This in turn causes the offset voltage to increase. On the other hand, when the common-mode input voltages V.sub.i.sup.+, V.sub.i.sup.- are lowered to a level nearly equal to the source DC bias V.sub.SS, the NMOS transistors 105, 106 will be switched OFF. This causes the circuit to lose the capability to maintain the offset voltage within the desired range.